@article{howe_martinoli_oswald_regazzoni_2021, 
  title={Exploring Parallelism to Improve the Performance of FrodoKEM in Hardware}, 
  DOI={10.1007/s13389-021-00258-7}, 
  abstractNote={<jats:title>Abstract</jats:title><jats:p>FrodoKEM is a lattice-based key encapsulation mechanism, currently a semi-finalist in NIST's post-quantum standardisation effort. A condition for these candidates is to use NIST standards for sources of randomness (i.e. seed-expanding), and as such most candidates utilise SHAKE, an XOF defined in the SHA-3 standard. However, for many of the candidates, this module is a significant implementation bottleneck. Trivium is a lightweight, ISO standard stream cipher which performs well in hardware and has been used in previous hardware designs for lattice-based cryptography. This research proposes optimised designs for FrodoKEM, concentrating on high throughput by parallelising the matrix multiplication operations within the cryptographic scheme. This process is eased by the use of Trivium due to its higher throughput and lower area consumption. The parallelisations proposed also complement the addition of first-order masking to the decapsulation module. Overall, we significantly increase the throughput of FrodoKEM; for encapsulation we see a <jats:inline-formula><jats:alternatives><jats:tex-math>$$16\times $$</jats:tex-math><mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML">
                <mml:mrow>
                  <mml:mn>16</mml:mn>
                  <mml:mo>×</mml:mo>
                </mml:mrow>
              </mml:math></jats:alternatives></jats:inline-formula> speed-up, achieving 825 operations per second, and for decapsulation we see a <jats:inline-formula><jats:alternatives><jats:tex-math>$$14\times $$</jats:tex-math><mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML">
                <mml:mrow>
                  <mml:mn>14</mml:mn>
                  <mml:mo>×</mml:mo>
                </mml:mrow>
              </mml:math></jats:alternatives></jats:inline-formula> speed-up, achieving 763 operations per second, compared to the previous state of the art, whilst also maintaining a similar FPGA area footprint of less than 2000 slices.
</jats:p>}, 
  publisher={Springer Science and Business Media LLC}, 
  author={Howe, James and Martinoli, Marco and Oswald, Elisabeth and Regazzoni, Francesco}, 
  year={2021}, 
  month={Mar}
  }