Abstract
This paper presents a side-channel analysis of the bitstream encryption mechanism provided by Xilinx Virtex FPGAs. This work covers our results analyzing the Virtex-4 and Virtex-5 family showing that the encryption mechanism can be completely broken with moderate effort. The presented results provide an overview of a practical real-world analysis and should help practitioners to judge the necessity to implement side-channel countermeasures. We demonstrate sophisticated attacks on off-the-shelf FPGAs that go far beyond schoolbook attacks on 8-bit AES S-boxes. We were able to perform the key extraction by using only the measurements of a single power-up. Access to the key enables cloning and manipulating a design, which has been encrypted to protect the intellectual property and to prevent fraud. As a consequence, the target product faces serious threats like IP theft and more advanced attacks such as reverse engineering or the introduction of hardware Trojans. To the best of our knowledge, this is the first successful attack against the bitstream encryption of Xilinx Virtex-4 and Virtex-5 reported in open literature.
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References
Side-channel Attack Standard Evaluation Board (SASEBO-GII). Further information is available via, http://staff.aist.go.jp/akashi.satoh/SASEBO/en/board/sasebo-g2.html
Braeken, A., Kubera, S., Trouillez, F., Touhafi, A., Mentens, N., Vliegen, J.: Secure FPGA Technologies and Techniques. In: FPL 2009, pp. 560–563. IEEE (2009)
Brier, E., Clavier, C., Olivier, F.: Correlation Power Analysis with a Leakage Model. In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol. 3156, pp. 16–29. Springer, Heidelberg (2004)
Drimer, S.: Security for volatile FPGAs. PhD thesis, Computer Laboratory, University of Cambridge, United Kingdom (2009)
Eisenbarth, T., Kasper, T., Moradi, A., Paar, C., Salmasizadeh, M., Shalmani, M.T.M.: On the Power of Power Analysis in the Real World: A Complete Break of the KeeLoq Code Hopping Scheme. In: Wagner, D. (ed.) CRYPTO 2008. LNCS, vol. 5157, pp. 203–220. Springer, Heidelberg (2008)
Gierlichs, B., Batina, L., Tuyls, P., Preneel, B.: Mutual Information Analysis. In: Oswald, E., Rohatgi, P. (eds.) CHES 2008. LNCS, vol. 5154, pp. 426–442. Springer, Heidelberg (2008)
Kepa, K., Morgan, F., Kosciuszkiewicz, K., Braun, L., Hübner, M., Becker, J.: FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. In: Becker, J., Woods, R., Athanas, P., Morgan, F. (eds.) ARC 2009. LNCS, vol. 5453, pp. 62–73. Springer, Heidelberg (2009)
Kocher, P.C., Jaffe, J., Jun, B.: Differential Power Analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999)
Messerges, T.S., Dabbish, E.A., Sloan, R.H.: Investigations of Power Analysis Attacks on Smartcards. In: USENIX Workshop on Smartcard, pp. 151–161. USENIX Association (1999)
Moradi, A., Barenghi, A., Kasper, T., Paar, C.: On the vulnerability of FPGA bitstream encryption against power analysis attacks: extracting keys from xilinx Virtex-II FPGAs. In: CCS 2011, pp. 111–124. ACM (2011)
Nohl, K., Evans, D., Starbug, Plötz, H.: Reverse-Engineering a Cryptographic RFID Tag. In: USENIX Security Symposium, pp. 185–194. USENIX Association (2008)
Note, J.-B., Rannaud, É.: From the Bitstream to the Netlist. In: FPGA 2008, p. 264. ACM (2008)
NVidia. NVIDIA’s Next Generation CUDA Compute Architecture: Fermi (2009), http://www.nvidia.com/content/PDF/fermi_white_papers/NVIDIAFermiComputeArchitectureWhitepaper.pdf
Nvidia. CUDA Developer Zone (Website) (2011), http://developer.nvidia.com/category/zone/cuda-zone
Oswald, D., Paar, C.: Breaking Mifare DESFire MF3ICD40: Power Analysis and Templates in the Real World. In: Preneel, B., Takagi, T. (eds.) CHES 2011. LNCS, vol. 6917, pp. 207–222. Springer, Heidelberg (2011)
Trimberger, S.: Trusted design in FPGAs. In: DAC 2007, pp. 5–8. ACM (2007)
Xilinx, Inc. Virtex-II Pro and Virtex-II Pro X FPGA User Guide (2002), http://www.xilinx.com/support/documentation/user_guides/ug012.pdf
Xilinx, Inc. Application Note XAPP151 (v1.7), Virtex Series Configuration Architecture User Guide (2004), http://www.xilinx.com/support/documentation/application_notes/xapp151.pdf
Xilinx, Inc. Virtex-4 FF668 Evaluation Board (2004), http://www.xilinx.com/products/boards-and-kits/HW-AFX-FF668-400.htm , User Guide, http://www.xilinx.com/support/documentation/boards_and_kits/ug078.pdf
Xilinx, Inc. Virtex-4 FPGA Configuration User Guide (2004), http://www.xilinx.com/support/documentation/user_guides/ug071.pdf
Xilinx, Inc. Application Note XAPP138 (v2.8), Virtex FPGA Series Configuration and Readback (2005), http://www.xilinx.com/support/documentation/application_notes/xapp138.pdf
Xilinx, Inc. Virtex-5 FPGA Configuration User Guide (2006), http://www.xilinx.com/support/documentation/user_guides/ug191.pdf
Ziener, D., Assmus, S., Teich, J.: Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. In: FPL 2006, pp. 1–6. IEEE (2006)
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Moradi, A., Kasper, M., Paar, C. (2012). Black-Box Side-Channel Attacks Highlight the Importance of Countermeasures. In: Dunkelman, O. (eds) Topics in Cryptology – CT-RSA 2012. CT-RSA 2012. Lecture Notes in Computer Science, vol 7178. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-27954-6_1
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DOI: https://doi.org/10.1007/978-3-642-27954-6_1
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