S. Katkoori
- 1.Paul E. Landman and Jan M. Rabaey, "Activity-Sensitive Architectural Power Analysis for the Control Path", 1995 International Symposium on Low Power Design, pp 93-98, April 995. Google Scholar
Digital Library
- 2.Nand Kumar, Srinivas Katkoori, Leo Rader and Ranga Vemuri, "Profile-Driven Behavioral Synthesis for Low Power VLSI Systems", IEEE Design ~_t Test of Computers, pp. 70-84, Fall 1995. Google ScholarDigital Library
- 3.Srinivas Katkoori and Ranga Vemuri, "Architectural Power Estimation Based on Behavioral Profiling", To appear in the Special Issue on Low Power Design, Journal on VLSI DE- SIGN, 1996.Google Scholar
- 4.F.N.Najm, "A Survey of Power Estimation Techniques in VLSI circuits", IEEE Transactions VLSI Systems, vol. 2, no. 4, pp. 446-455, January 1995. Google ScholarDigital Library
- 5.R. Brayton, G. Hachtel, C. McMullen, and A. Sangiovanni- Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, 1984. Google ScholarDigital Library
- 6.Srinivas Katkoori, Nand Kumar and Ranga Vemuri, "High Level Profiling Based Low Power Synthesis Technique", Proceedings of International Conference on Computer Design 1995, Austin, October 2-5, pp. 759-765, 1995. Google ScholarDigital Library
Index Terms
- Simulation based architectural power estimation for PLA-based controllers
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