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"PERI: A Configurable Posit Enabled RISC-V Core."

Sugandha Tiwari et al. (2021)

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DOI: 10.1145/3446210

access: open

type: Journal Article

metadata version: 2021-07-15

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  - journals/taco/TiwariGRK21
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  - https://dblp.org/rec/journals/taco/TiwariGRK21
Sugandha Tiwari, Neel Gala, Chester Rebeiro, V. Kamakoti:
PERI: A Configurable Posit Enabled RISC-V Core. ACM Trans. Archit. Code Optim. 18(3): 25:1-25:26 (2021)

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