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ORCIDCliff C. N. Sze
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- affiliation: Texas A&M University, College Station, Texas, USA
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2010 – 2019
- 2017
[j20]Johann Knechtel, Ozgur Sinanoglu
, Ibrahim Abe M. Elfadel, Jens Lienig, Cliff C. N. Sze:
Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration. IPSJ Trans. Syst. LSI Des. Methodol. 10: 45-62 (2017)- [c46]He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu, Cliff C. N. Sze:
Fast and Highly Scalable Bayesian MDP on a GPU Platform. BCB 2017: 158-167 - 2016
- [j19]Tiago Reimann, Cliff C. N. Sze, Ricardo Reis:
Challenges of cell selection algorithms in industrial high performance microprocessor designs. Integr. 52: 347-354 (2016) - [c45]He Zhou, Jiang Hu, Sunil P. Khatri, Frank Liu, Cliff C. N. Sze, Mohammadmahdi R. Yousefi:
GPU acceleration for Bayesian control of Markovian genetic regulatory networks. BHI 2016: 304-307 - [c44]Tiago J. Reimann, Cliff C. N. Sze, Ricardo Reis:
Cell Selection for High-Performance Designs in an Industrial Design Flow. ISPD 2016: 65-72 - 2015
- [j18]Azadeh Davoodi, Jiang Hu, Muhammet Mustafa Ozdal, Cliff C. N. Sze:
Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 501 (2015) - [j17]Yici Cai, Chao Deng, Qiang Zhou, Hailong Yao, Feifei Niu, Cliff N. Sze:
Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 142-155 (2015) - [c43]Tiago Reimann, Cliff C. N. Sze, Ricardo Reis:
Gate sizing and threshold voltage assignment for high performance microprocessor designs. ASP-DAC 2015: 214-219 - 2014
- [j16]Cheng-Kok Koh, Chin Ngai Sze:
Guest Editorial Special Section on Contemporary and Emerging Issues in Physical Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 493-494 (2014) - [j15]Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar:
Techniques for scalable and effective routability evaluation. ACM Trans. Design Autom. Electr. Syst. 19(2): 17:1-17:37 (2014) - [c42]Nancy Y. Zhou, Phillip J. Restle, Joseph N. Palumbo, Joseph N. Kozhaya, Haifeng Qian, Zhuo Li, Charles J. Alpert, Cliff C. N. Sze:
Pacman: driving nonuniform clock grid loads for low-skew robust clock network. SLIP 2014: 3:1-3:5 - [e2]Cliff C. N. Sze, Azadeh Davoodi:
International Symposium on Physical Design, ISPD'14, Petaluma, CA, USA, March 30 - April 02, 2014. ACM 2014, ISBN 978-1-4503-2592-9 [contents] - 2013
- [c41]Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert:
Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths. ASP-DAC 2013: 350-355 - [c40]Wen-Hao Liu, Yaoguang Wei, Cliff C. N. Sze, Charles J. Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan:
Routing congestion estimation with real design constraints. DAC 2013: 92:1-92:8 - [c39]Yaoguang Wei, Zhuo Li, Cliff C. N. Sze, Shiyan Hu, Charles J. Alpert, Sachin S. Sapatnekar:
CATALYST: planning layer directives for effective design closure. DATE 2013: 1873-1878 - [c38]Thomas H. Osiecki, Min-Yu Tsai, Anne E. Gattiker, Damir A. Jamsek, Sani R. Nassif, William Evan Speight, Cliff C. N. Sze:
Hardware Acceleration of an Efficient and Accurate Proton Therapy Monte Carlo. ICCS 2013: 2241-2250 - [c37]Samuel I. Ward, Natarajan Viswanathan, Nancy Y. Zhou, Cliff C. N. Sze, Zhuo Li, Charles J. Alpert, David Z. Pan:
Clock power minimization using structured latch templates and decision tree induction. ICCAD 2013: 599-606 - [c36]Cliff C. N. Sze, Laleh Behjat, Nikhil Jayakumar, Atul Walimbe, Gregory Ford, Mark Zwolinski, Harish Dangat, Giriraj Kakol:
ISPD 2013 expert designer/user session (eds). ISPD 2013: 137 - [e1]Cheng-Kok Koh, Cliff C. N. Sze:
International Symposium on Physical Design, ISPD'13, Stateline, NV, USA, March 24-27, 2013. ACM 2013, ISBN 978-1-4503-1954-6 [contents] - 2012
- [j14]Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze:
Postgrid Clock Routing for High Performance Microprocessor Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 255-259 (2012) - [c35]Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Cliff C. N. Sze, Natarajan Viswanathan, Nancy Y. Zhou:
Guiding a physical design closure system to produce easier-to-route designs with more predictable timing. DAC 2012: 465-470 - [c34]Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar:
GLARE: global and local wiring aware routability evaluation. DAC 2012: 768-773 - [c33]Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei:
The DAC 2012 routability-driven placement contest and benchmark suite. DAC 2012: 774-782 - [c32]Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert:
WRIP: logic restructuring techniques for wirelength-driven incremental placement. ACM Great Lakes Symposium on VLSI 2012: 327-332 - [c31]Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze, Natarajan Viswanathan, Samuel I. Ward:
Placement: Hot or Not? ICCAD 2012: 283-290 - [c30]Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei:
ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite. ICCAD 2012: 345-348 - 2011
- [j13]Joshua Friedrich, Ruchir Puri, Uwe Brandt, Markus Bühler, Jack DiLullo, Jeremy Hopkins, Mozammel Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, Douglass Lamb, Alice Lee, Frank Musante, Jens Noack, Peter J. Osler, Stephen D. Posluszny, Haifeng Qian, Shyam Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, Benjamin R. Russell, Cliff C. N. Sze, Gustavo E. Téllez:
Design methodology for the IBM POWER7 microprocessor. IBM J. Res. Dev. 55(3): 9 (2011) - [j12]David A. Papa, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Natarajan Viswanathan, Gi-Joon Nam, Igor L. Markov:
Physical Synthesis with Clock-Network Optimization for Large Systems on Chips. IEEE Micro 31(4): 51-62 (2011) - [j11]Nancy Ying Zhou, Charles J. Alpert, Zhuo Li, Cliff N. Sze, Louise Trevillyan:
Shedding Physical Synthesis Area Bloat. VLSI Design 2011: 503025:1-503025:10 (2011) - [c29]Michael D. Moffitt, Chin Ngai Sze:
Wire synthesizable global routing for timing closure. ASP-DAC 2011: 545-550 - [c28]Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin Ngai Sze:
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. ACM Great Lakes Symposium on VLSI 2011: 199-204 - [c27]Cliff C. N. Sze:
The future of clock network synthesis. ICCAD 2011: 270 - [c26]Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze:
Grid-to-ports clock routing for high performance microprocessor designs. ISPD 2011: 21-28 - [c25]Samuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr.:
Quantifying academic placer performance on custom designs. ISPD 2011: 91-98 - [c24]Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Gi-Joon Nam, Jarrod A. Roy:
The ISPD-2011 routability-driven placement contest and benchmark suite. ISPD 2011: 141-146 - 2010
- [c23]Shayak Banerjee, Kanak B. Agarwal, Chin Ngai Sze, Sani R. Nassif, Michael Orshansky:
A methodology for propagating design tolerances to shape tolerances for use in manufacturing. DATE 2010: 1273-1278 - [c22]Zhuo Li, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou:
Ultra-fast interconnect driven cell cloning for minimizing critical path delay. ISPD 2010: 75-82 - [c21]Cliff C. N. Sze:
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results. ISPD 2010: 143
2000 – 2009
- 2009
- [c20]Cliff N. Sze, Phillip J. Restle, Gi-Joon Nam, Charles J. Alpert:
Ispd2009 clock network synthesis contest. ISPD 2009: 149-150 - 2008
- [j10]David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov:
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2156-2168 (2008) - [c19]Tao Luo, David A. Papa, Zhuo Li, Chin Ngai Sze, Charles J. Alpert, David Z. Pan:
Pyramids: an efficient computational geometry-based approach for timing-driven placement. ICCAD 2008: 204-211 - [c18]David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov:
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. ISPD 2008: 2-9 - [c17]Gi-Joon Nam, Cliff C. N. Sze, Mehmet Can Yildiz:
The ISPD global routing benchmark suite. ISPD 2008: 156-159 - [r2]Jiang Hu, Gabriel Robins, Cliff C. N. Sze:
Timing-Driven Interconnect Synthesis. Handbook of Algorithms for Physical Design Automation 2008 - [r1]Jiang Hu, Cliff C. N. Sze:
Buffering in the Layout Environment. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [b1]Chin Ngai Sze:
Algorithms for the scaling toward nanometer VLSI physical synthesis. Texas A&M University, College Station, USA, 2007 - [j9]Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz:
Techniques for Fast Physical Synthesis. Proc. IEEE 95(3): 573-599 (2007) - [j8]Chin Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Path-Based Buffer Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1346-1355 (2007) - [j7]Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin Ngai Sze:
Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2009-2022 (2007) - [c16]Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz:
The nuts and bolts of physical synthesis. SLIP 2007: 89-94 - 2006
- [j6]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze:
Accurate estimation of global buffer delay within a floorplan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1140-1145 (2006) - [c15]Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze:
Fast algorithms for slew constrained minimum cost buffering. DAC 2006: 308-313 - [c14]Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang:
Timing-driven Steiner trees are (practically) free. DAC 2006: 389-392 - [c13]Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze:
Integrated placement and skew optimization for rotary clocking. DATE 2006: 756-761 - 2005
- [j5]Yongqiang Lu, Chin Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Navigating Register Placement for Low Power Clock Network Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3405-3411 (2005) - [c12]Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Making fast buffer insertion even faster via approximation techniques. ASP-DAC 2005: 13-18 - [c11]Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Register placement for low power clock network. ASP-DAC 2005: 588-593 - [c10]Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu:
Skew scheduling and clock routing for improved tolerance to process variations. ASP-DAC 2005: 594-599 - [c9]Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Navigating registers in placement for clock network minimization. DAC 2005: 176-181 - [c8]Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Path based buffer insertion. DAC 2005: 509-514 - 2004
- [j4]Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze:
Porosity-aware buffered Steiner tree construction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 517-526 (2004) - [j3]Cliff C. N. Sze, Ting-Chi Wang, Li-C. Wang:
Multilevel circuit clustering for delay minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 1073-1085 (2004) - [c7]Cliff C. N. Sze, Jiang Hu, Charles J. Alpert:
A place and route aware buffered Steiner tree construction. ASP-DAC 2004: 355-360 - [c6]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze:
Accurate estimation of global buffer delay within a floorplan. ICCAD 2004: 706-711 - 2003
- [j2]Cliff C. N. Sze, Ting-Chi Wang:
Optimal circuit clustering for delay minimization under a more general delay model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 646-651 (2003) - [c5]Chin Ngai Sze, Ting-Chi Wang:
Performance-driven multi-level clustering for combinational circuits. ASP-DAC 2003: 729-740 - 2002
- [j1]Chin Ngai Sze, Wangning Long, Yu-Liang Wu, Jinian Bian:
Accelerating Logic Rewiring Using Implication Analysis Tree. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2725-2736 (2002) - [c4]Cliff C. N. Sze, Ting-Chi Wang:
Optimal circuit clustering with variable interconnect delay. ISCAS (4) 2002: 707-710 - [c3]Cliff C. N. Sze, Ting-Chi Wang:
Multi-Level Circuit Clustering for Delay Minimization. IWLS 2002: 227-232 - 2001
- [c2]Chin Ngai Sze, Yu-Liang Wu:
Improved alternative wiring scheme applying dominator relationship. ASP-DAC 2001: 473-478 - 2000
- [c1]Yu-Liang Wu, Chin Ngai Sze, Chak-Chung Cheung, Hongbing Fan:
On improved graph-based alternative wiring scheme for multi-level logic optimization. ICECS 2000: 654-657
Coauthor Index
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