IEICE Trans - A Power Analysis Attack Countermeasure Based on Random Data Path Execution For CGRA

A Power Analysis Attack Countermeasure Based on Random Data Path Execution For CGRA

Wei GE
Shenghua CHEN
Benyu LIU
Min ZHU
Bo LIU

Publication
IEICE TRANSACTIONS on Information and Systems Vol.E103-D No.5 pp.1013-1022
Publication Date: 2020/05/01
Publicized: 2020/02/10
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2019EDP7308
Type of Manuscript: PAPER
Category: Computer System
Keyword:
side-channel attack, reconfigurable architecture, differential power analysis, power trace,

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Summary:
Side-channel Attack, such as simple power analysis and differential power analysis (DPA), is an efficient method to gather the key, which challenges the security of crypto chips. Side-channel Attack logs the power trace of the crypto chip and speculates the key by statistical analysis. To reduce the threat of power analysis attack, an innovative method based on random execution and register randomization is proposed in this paper. In order to enhance ability against DPA, the method disorders the correspondence between power trace and operands by scrambling the data execution sequence randomly and dynamically and randomize the data operation path to randomize the registers that store intermediate data. Experiments and verification are done on the Sakura-G FPGA platform. The results show that the key is not revealed after even 2 million power traces by adopting the proposed method and only 7.23% slices overhead and 3.4% throughput rate cost is introduced. Compared to unprotected chip, it increases more than 4000× measure to disclosure.

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