Chuanjun Zhang
ABSTRACT
Static energy dissipation in cache memories will constitute an increasingly larger portion of total microprocessor energy dissipation due to nanoscale technology characteristics and the large size of on-chip caches. We propose to reduce the static energy dissipation of an on-chip data cache by taking advantage of the frequent values (FV) that widely exist in a data cache memory. The original FV-based low-power cache design aimed at only reducing dynamic power, at the cost of a 5% slowdown. We propose a better design that reduces both static and dynamic cache power, and that uses a circuit design that eliminates performance overhead. A designer can utilize our architecture by simulating an application and then synthesizing the FVs into an application-specific FV cache design when values will not change, or by simulating and then writing to an FV-cache with configuration registers when values could change. Furthermore, we describe hardware that can dynamically determine FVs and write to the configuration registers completely transparently. Experiments on 11 Spec 2000 benchmarks show that, in addition to the dynamic power savings, 33% static energy savings for data caches can be achieved.
- {1} A. Agarwal, H. Li, and K. Roy, "DRG-Cache: A Data Retention Gated-Ground Cache for Low Power," Design Automation Conf., June 2002. Google Scholar
Digital Library
- {2} D. H. Albonesi, "Selective Cache Ways: On-Demand Cache Resource Allocation," Journal of Instruction Level Parallelism, May 2000.Google Scholar
- {3} D. Burger and T. M. Austin, "The SimpleScalar Tool Set, Version 2.0," Univ. of Wisconsin-Madison Computer Sciences Dept. Technical Report #1342, June 1997. Google ScholarDigital Library
- {4} K. Ghose and M. B. Kamble, "Reducing Power in Superscalar Processor Caches using Subbanking, Multiple Line Buffers, and Bit Line Segmentation," IEEE/ACM Int. Symp. on Low Power Electronics and Design, 1999. Google ScholarDigital Library
- {5} S. Gunther and S. Rajgopal, Personal communication.Google Scholar
- {6} M. Huang, J. Renau, S. M. Yoo, and J. Torrellas, "L1 Data Cache ecomposition for Energy Efficiency," Int. Symp. on Low Power Electronics and Design, 2001. Google ScholarDigital Library
- {7} http://www.specbench.org/osg/cpu2000/Google Scholar
- {8} K. Inoue, T. Ishihara, and K. Murakami, "Way-Predictive Set-Associative Cache for High Performance and Low Energy Consumption," Int. Symp. On Low Power Electronics and Design, 1999. Google ScholarDigital Library
- {9} N. S. Kim, K. Flautner, D. Blaauw, T. Mudge, "Drowsy Instruction Caches, Leakage Power Reduction using Dynamic Voltage Scaling and Cache Sub-bank Prediction," Int. Symp. on Microarchitecture, Nov. 2002. Google ScholarDigital Library
- {10} J. Kin, M. Gupta and W. Mangione-Smith, "The Filter Cache: An Energy Efficient Memory Structure," Int. Symp. on Microarchitecture, pp. 184-193, Dec. 1997. Google ScholarDigital Library
- {11} S. Kaxiras, Z. Hu, and M. Martonosi, "Cache Decay: Exploiting General Behavior to Reduce Cache Leakage Power," Int. Symp. on Computer Architecture, 2001. Google ScholarDigital Library
- {12} J. Montenaro. et al., "A 160MHz 32b 0.5W CMOS RISC Microprocessor," Int. Solid-State Circuits Conf., 1996.Google Scholar
- {13} M. Powell, S. H. Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar. Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories. Int. Symp. on Low Power Electronics and Design, 2000. Google ScholarDigital Library
- {15} P. Ranganathan, S. Adve, and N. P. Jouppi, "Reconfigurable Caches and their Application to Media Processing," Int. Symp. on Computer Architecture, 2000. Google ScholarDigital Library
- {15} P. Shivakumar, N. Jouppi, "CACTI 3.0: An Integrated Cache Timing, Power, and Area Model", COMPAQ Western Research Lab, 2001.Google Scholar
- {16} J. Yang and R. Gupta, "Energy Efficient Frequent Value Data Cache Design," Int. Symp. on Microarchitecture, Nov. 2002. Google ScholarDigital Library
- {17} J. Yang, and R. Gupta, "Frequent Value Locality and its Applications," ACM Transactions on Embedded Computing Systems (inaugural issue), Vol. 1, No. 1, pages 79-105, November 2000. Google ScholarDigital Library
- {18} C. Zhang, F. Vahid, and W. Najjar "A Highly Configurable Cache Architecture for Embedded Systems," Int. Symp. on Computer Architecture, June 2003. Google ScholarDigital Library
- {19} H. Zhou, M. C. Toburen, E. Rotenberg, T. M. Cont. Adaptive mode-control: A static-power-efficient cache design. In the 10th Intl. Conf. on Parallel Architectures and Compilation Techniques, 2000. Google ScholarDigital Library
Index Terms
- Low Static-Power Frequent-Value Data Caches
Recommendations
Compiler-managed partitioned data caches for low power
LCTES '07: Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systemsSet-associative caches are traditionally managed using hardware-based lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailored to the application's memory needs, thus enabling optimal use of this ...
A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches
ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and designChip multiprocessors (CMPs) emerge as a dominant architectural alternative in high-end embedded systems. Since off-chip accesses require a long latency and consume a large amount of power, CMPs are typically based on multiple levels of on-chip cache ...
Compiler-managed partitioned data caches for low power
Proceedings of the 2007 LCTES conferenceSet-associative caches are traditionally managed using hardware-based lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailored to the application's memory needs, thus enabling optimal use of this ...
Comments