XianWei Zhang
ABSTRACT
The emerging Phase Change Memory (PCM), while having many advantages, suffers from slow write operations. This is mainly due to its asymmetric write characteristic, i.e., for two types of write operations of PCM, SET is much slower than RESET. Recent study has shown that proactively setting dirty memory lines to all '1's can enable RESET-only writes when these lines are written back from the cache, which helps to reduce the effective write latency. Unfortunately, it results in higher write power demand. In this paper, we propose WoM-SET, a low power proactive-SET-based write strategy. By exploiting the WoM (write-once memory) code, we greatly reduce the number of RESETs per write and hence the write power demand. By applying our design only to write-intensive pages, we restrict the extra space requirement in WoM-SET. Our experiments show that WoM-SET achieves 40% RESET bit reduction, 40% write power reduction, and 12% energy-delay-product improvement over the PreSET scheme.
- S. Chhabra and Y. Solihin, "i-NVMM: A Secure Non-Volatile Main Memory System with Incremental Encryption," in ISCA, 2011. Google Scholar
Digital Library
- S. Cho and H. Lee, "Flip-N-Write: A Simple Deterministic Technique to Improve PRAM Write Performance, Energy and Endurance," in MICRO, 2009. Google ScholarDigital Library
- Y. Choi, et. al., "A 20nm 1.8V 8Gb PRAM with 40MB/s Program Bandwidth," in ISSCC, 2012.Google Scholar
- K. Fang, et. al., "Memory Architecture for Integrating Emerging Memory Technologies," in PACT, 2011. Google ScholarDigital Library
- G. D. Forney, "Coset Codes. I. Introduction and Geometrical Classification," in IEEE Trans. Info. Theory, 34(5), 2009. Google ScholarDigital Library
- ITRS, "The International Technology Roadmap for Semiconductors Report 2009," 2009, http://www.itrs.net/.Google Scholar
- A. N. Jacobvitz, et. al., "Coset Coding to Improve the Lifetime of Memory," in HPCA, 2013. Google ScholarDigital Library
- A. Jiang, "On the Generalization of Error-correcting WOM Codes," in ISIT, 2007.Google Scholar
- L. Jiang, et. al., "Improving Write Operations in MLC Phase Change Memory," in HPCA, 2012. Google ScholarDigital Library
- K. Kim and S. J. Ahn, "Reliability Investigations for Manufacturable High Density PRAM," in IRPS, 2005.Google Scholar
- B. C. Lee, et. al., "Architecting Phase Change Memory as a Scalable DRAM Alternative," in ISCA, 2009. Google ScholarDigital Library
- M. K. Qureshi, et. al., "Enhancing Lifetime and Security of PCM-based Main Memory with Start-Gap Wear Leveling," in MICRO, 2009. Google ScholarDigital Library
- M. K. Qureshi, et. al., "Scalable High Performance Main Memory System Using Phase-Change Memory Technology," in ISCA, 2009. Google ScholarDigital Library
- M. K. Qureshi, et. al., "Improving Read Performance of Phase Change Memories via Write Cancellation and Write Pausing," in HPCA, 2010.Google Scholar
- M. K. Qureshi, et. al., "PreSET: Improving Read Write Performance of Phase Change Memories by Exploiting Asymmetry in Write Times," in ISCA, 2012. Google ScholarDigital Library
- B. Rajendran, et. al., "Analytical Model for Reset Operation of Phase Change Memor," in IEDM, 2008.Google Scholar
- S. Raoux, et. al., "Phase-change Random Access Memory: A Scalable Technology," IBM J. RES. & DEV., 2008. Google ScholarDigital Library
- R. L. Rivest and A. Shamir, "How to Reuse a Write-Once Memory," InC, 1982.Google Scholar
- S. Schechter, et. al., "Use ECP, not ECC, for Hard Failures in Resistive Memories," in ISCA, 2010. Google ScholarDigital Library
- N. H. Seong, et. al., "Security Refresh: Prevent Malicious Wear-out and Increase Durability for Phase-change Memory with Dynamically Randomized Address Mapping," in ISCA, 2010. Google ScholarDigital Library
- E. Yaakobi, et. al., "Multiple-write WOM-codes," in Allerton, 2010.Google Scholar
- E. Yaakobi, et. al., "Error Characterization and Coding Schemes for Flash Memories," in ACTEMT workshop, 2010.Google Scholar
- D. H. Yoon, et. al., "FREE-p: Protecting Non-volatile Memory against Both Hard and Soft Errors," in HPCA, 2011. Google ScholarDigital Library
- P. Zhou, et. al., "A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology," in ISCA, 2009. Google ScholarDigital Library
Index Terms
- WoM-SET: low power proactive-SET-based PCM write using WoM code
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