Hao Xu
ABSTRACT
Ever since the invention of various leakage power reduction techniques, leakage and dynamic power reduction techniques are categorized into two separate sets. Most of them cannot be applied together during runtime. The gap between them is due to the large energy breakeven time (EBT) and wake-up time (WUT) of conventional leakage reduction techniques. This paper proposes a new leakage reduction technique (SLITH) based on Vth hopping. SLITH has very low EBT and WUT, yet keeps the effectiveness of leakage reduction. Thus, it is able to reduce the gap, and enables joint dynamic and leakage power reduction. SLITH can be applied together with clock gating, precomputation and operand isolation etc., and significantly reduces both dynamic and active leakage power consumption.
- K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer cmos circuits," in IEEE, Feb. 2003, pp. 305--327.Google Scholar
Cross Ref
- J. Tschanz, S. Narendra, Y. Ye, B. Bloechel, S. Borkar, and V. De, "Dynamic sleep transistor and body bias for active leakage power control of microprocessors," IEEE J. Solid-State Circuits, vol. 38, pp. 1838--1845, Nov. 2003.Google ScholarCross Ref
- A. Abddollahi, M. Pedarm, F. Fallah, and I. Ghosh, "Precomputation-based guarding for dynamic and leakage power reduction," in ICCD, Oct. 2003, pp. 90--97. Google ScholarDigital Library
- K.-S. Min, H.-D. Choi, H.-Y. Choi, H. Kawaguchi, and T. Sakurai, "Leakage-suppressed clock-gating circuit with zigzag super cut-off cmos (zsccmos) for leakage-dominant sub-70-nm and sub-1-v-v/sub dd/lsis," IEEE Trans. VLSI Syst., vol. 14, pp. 430--435, Apr. 2006. Google ScholarDigital Library
- H. Xu, R. Vemuri, and W.-B. Jone, "Run-time active leakage reduction by power gating and reverse body biasing: An energy view," in ICCD, Oct. 2008.Google Scholar
- H. Singh, K. Agarwal, D. Sylvester, and K. Nowka, "Enhanced leakage reduction techniques using intermediate strength power gating," IEEE Trans. VLSI Syst., vol. 15, pp. 1215--1224, Nov. 2007. Google ScholarDigital Library
- A. S. University. Predictive technology model. {Online}. Available: http://www.eas.asu.edu/ptm/Google Scholar
- Selective light Vth hopping (SLITH): bridging the gap between runtime dynamic and leakage power reduction
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